This hardware is usually implemented in Field Programmable Gate Arrays (FGPAs) or as dedicated Application-specific Integrated Circuits (ASICs). Digital Down Conversion (DDC) is a "Software Radio" application, where the goal is to move an analogue processing task into the digital domain.The application is very data-intensive, but the operations are generally highly repetitive. Full analogue down conversion requires analogue multiplication of the received signal with the radio frequency carrier. This results in “frequency shifting” the signal down to baseband, so that the signal bandwidth of interest is now below half the sampling rate of the Analog-to-Digital Converter (ADC). A low pass filter is required to prevent aliasing due to other signals outwith the band of interest. Once in the digital domain, there may be some further processing to extract the information of interest.
Software implementations are uncommon, but DDCarchitectural components can be very efficiently implemented in hardware. By comparing this with a software implementation, HPC software engineers can understand how FPGA technology is most likely to give performance improvements and power savings.
It is not always possible to directly sample at a high enough frequency to perform the whole down conversion process digitally. In this case, an initial wideband down conversion is used to bring the signal down to an intermediate frequency. This may especially be the case if there are a number of channels within a band of interest. The intermediate band signal is then sampled into the digital domain and (often several) digital down converters may frequency-shift the signal further. As the data bandwidth of the output is much lower, these filters will also down sample the signal, to a manageable bandwidth.
Modern ADCs now work with sample rates in the GHz range, so in some cases it may be possible to directly sample at the radio frequency. The ADC could then perform all the down conversion in the digital domain. This would require significant digital processing performance - which would increase power usage and cost.
The example code in the case study implements down conversion from intermediate frequency. The input data stream therefore consists of two channels of sampled fixed-point data. The code allows all bit widths to be configured at synthesis time, but we will use 16 point signed integers for easier comparison with processor-based implementations. Typically the input bit width will depend on the ADC characteristics and is likely to be less than 16 bits.