The designs for the Adept Power Measurement Infrastructure are open-source and available for download here.
|ADEPT-POWER-SENSE, ADEPT XRM Sensor Adaptor||Diagrams of the Adept Sensor and Interface Boards (.pdf)|
|Sensor Board Data sheets||Documents describing the components of the Sensor and Interface Boards (.zip)|
|Sensor Board||Files related to the the operation of the Sensor Board (.zip)|
Files related to the the operation of the Interface Board (.zip)
|IPR, Block Design 1, Block Design 2||Firmware files (.zip) (Please download and fully unzip for all files)|
|Software||Software files including the OS and API (.zip)|
Further Information about each component is detailed below.
The Adept measurement system is based around the Alpha-Data ADM-XRC-7Z1, a Xilinx Zynq based FPGA SoC. The design, in its current state, is intended to drive up to ~80 power monitor boards, and therefore makes use of the large amount of DDR3 available to the Zynq’s programmable logic on the 7z1 for buffering data.
It would be possible to re-target the firmware design to other hardware platforms, such as off the shelf Zynq demo boards, by modifying the Vivado block design and swapping out the AXI4 MIG interface with other suitable buffering (i.e. block RAM).
The ADM-XRC-7Z1 uses a high density Samtec QSH connector, requiring an interface board to break these signals out to individual connectors for each ADC. The provided hardware interface board design could easily be swapped for a connector used on other boards (such as an FMC connector).
The interface board is configurable to use different sources of power, including 12V0 (provided from the 7Z1) or an external power jack (with centre pin negative).
The interface board also has some small design errors, requiring modification shown in the image (Interface_board_mod.png) in the interface board folder.
Power Monitor Board
The power monitor boards are based around the AD7982 ADC. The interface signals (SCK, SDO, CNV and SDI) are connected through LVDS buffers directly to the Samtec EHT series interface connectors. The boards will work between 0A-20A, and 2V-15V.
The power monitor board also has some small design errors, requiring modification, listed in the ECN folder.
The Adept IP project, containing the required source code to drive the ADCs, an AXI master interface for buffering data (i.e. for connecting to MIG or BRAM controller), and an OCP slave interface for low-speed register read/writes for control.
The IP project contains blocks necessary to: drive the ADC interface, store that data into a set of buffers in addressed memory (such as DDR or block RAM) through the master AXI port, and send interrupts to the Zynq’s processor once a buffer is full.
The IP block should be relatively hardware independent, and could easily be re-targeted to other FPGA platforms. It can drive multiple ADC chains (see AD7982 datasheet for description of the chaining) in parallel, configurable from 1 ADC chain. The maximum number of chain is a limit of the amount of LVDS IO available on the board, which for the ADM-XRC-7Z1 is 12 chains. The base address offset and a date stamp that’s readable from the control bust interface can be set. An extra option “C S00 Ocp Align” is optionally available to force the AXI master transactions to not cross 4k address boundaries, which is a requirement of the AXI specification.
Block Design Project
The block design project imports the IP design as a block, and allows easy connection between the Zynq’s processor, the FPGA blocks and external interfaces. This project is what defines the hardware-platform specific information, such as IO pin constraints, memory interfaces …etc, and should be modified as required to suit the target hardware.
The block design project is already configured such that it will produce a valid bitstream for the ADM-XRC-7Z1 hardware platform.
Software – OS
The OS running on the 7z1 is based on Yocto-Poky Linux, although the API should work with most Linux versions that run on the Zynq.
Software – API
The API is provided as a Netbeans project. The source files are also provided to allow the user to build with whichever IDE/OS is required.
The API consists of two parts: the “Datacard” API, which provides functions to access Alpha-Data’s FPGA boards, and the “Adeptsense” API, which uses the functions provided by the “Datacard” API to drive the FPGA firmware. The AdeptSense API provides the following functions:
GetSensorCount(): Returns the number of sensor boards that have been enabled.
GetChainCount(): Returns the total number of sensor chains available in the system.
SetTestPattern(): Enables the test pattern.
GetTime(): Gets the 64-bit timestamp counter (increments at 200MHz from zero at power on).
Start(): Starts recording data. Parameters are specified by means of control text files.
GetSensorDataBuffer(): Gets the next available data buffer. Can either wait until data is available (blocking) or return with no data if none is available.
ValidateSensorDataBuffer(): Checks the header of the data buffer to ensure that it is valid.
GetDataReadyCount(): Returns the total number of data buffers that have been made ready for reading. This can be compared with the number of data buffers that have actually been written to memory to ensure that no data has been dropped.
Stop(): Stops the ADCs and API.
Software – Example Application
There is an example application “Adeptraw” which initialises the API, starts the capture of data using parameters specified in the control files, either saves the data to file, or displays the raw data. The Adeptraw software has the following options:
-debug : prints extra debug messages
-pattern : forces the firmware to generate a known test pattern
-save : saves the recorded date to file
-fs : sets up the required file system required by the API.
-calibrate : Enters calibration mode. Calibration mode uses two-point calibraton, using a test load resistance and a precision meter to measure the voltage and current. The software will prompt the user to enter the serial number of the board, then the voltage/current values, then the user should change the voltage/current to a different value, and enter the new values. The API will save the calibration data as a comma separated text file with the card’s serial number as the file name.
The example application creates an “AAdeptPowerMonitor” Object, which: programs the FPGA, opens the interface to the FPGA and initialises the FPGA firmware. After this, Start() is called, followed by GetSensorDataBuffer() as required.